The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs.
One development in some IC designs has been the replacement of traditional polysilicon gates with high-k/metal gates (HK/MG). A typical HK/MG includes a high-k gate dielectric layer, a work function (WF) metal layer, and a low resistance metal filling layer. Such structure is supposed to improve transistor density and switching speed, while reducing switching power and gate leakage. As technology nodes continue shrinking, some difficulties in the fabrication of HK/MG arise. One of the difficulties is that the metal filling layer may have a small footprint, thus it is difficult for a gate contact to land on the metal filling layer properly.